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TRU-050 Frequency Translation



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THE COMPLETE PLL SOLUTION

TRU-050!
TRU-050

Flexible Modular Solution
A Quartz Stabilized PLL


It's a phased-locked loop ASIC with a quartz stabilized VCXO!


  It will:
  • Reduce:   
 design time    
  • Improve:   
 jitter performance
  component count     reliability
  board space      
 
  It performs:
  • Clock recovery & data retiming
  • Frequency translation
  • Clock smoothing
 
  In applications up to 65.536 Mb/s:
  • ATM, SONET/SDH
  • XDSL, Network communications
  • Digital audio/video, PBX systems
What Does It Do?
Vectron International's TRU-050 module is a user-configured, phase-locked loop (PLL) solution designed to simplify a wide variety of clock recovery and data retiming, frequency translation and clock smoothing applications. The device features a phase-lock loop ASIC with a quartz stabilized VCXO for superior stability and jitter performance. This highly integrated module provides unsurpassed performance, reliability and quality. The proprietary ASIC device includes a refined Phase Detector, a Loop Filter Op-Amp, a Loss of Signal Alarm with Clock Return to Nominal feature, a VCXO circuit, and an optional 2n Output Frequency Division circuit.

The ASIC and quartz resonator are housed in a hermetic 16-pin DIL ceramic package with optional thru-hole or surface mount leads. The VCXO frequency (OUT1) and division factor (OUT2) are factory set in accordance with customer specifications. PLL response is optimized for each application by the selection of three external passive components. Software is available from Vectron to aid in loop filter component selection and loop response modeling.
 
  Features:     Benefits:
PLL with quartz stabilized VCXO
Output jitter less than 20 ps
Loss of signal (LOS) alarm
Return to nominal clock upon LOS
Input data rates from 8 kb/s to 65.536 Mb/s
Surface mount option
Tri-state option
User defined PLL loop response
NRZ data compatible
Robust hermetic ceramic package
Single or +5.0V supply (+3.3V option available) 		  Flexible modular solution
Reduce design time
Increase circuit reliability
Less board space
Reduces component count


What's below...
Download:
 
Product Software
Download Loop Component Selection & Simulation Software
Download Instructions For Loop Component Selection & Simulation Software




Electrical Characteristics

Parameter
Symbol
Min
Max
Unit
Input NRZ Data Rates
DATAIN
0.008
65.536
MHz
Input RZ Data and Clock Rates1
DATAIN
0.016
32.768
MHz
Nominal Output Frequency:
     Output 1
     Output 22
OUT1
OUT2
14.0
0.05
65.536
32.768
MHz
MHz
Supply Voltage
VDD
4.5
5.5
V
Supply Current (VDD=4.5 V)
IDD
25
60
mA
Output Voltage Levels (VDD=4.5 V):
     Output Logic High3
     Output Logic Low3
VOH
VOL
2.5
-
-
0.5
V
V
Transition Times3:
     Rise Time (0.5 V to 2.5 V)
     Fall Time (2.5 V to 0.5 V)
tR
tF
0.5
0.5
5
5
ns
ns
Symmetry or Duty Cycle4:
     Output 1
     Output 22
     Recovered Clock
SYM1
SYM2
RCLK
40
45
40
60
55
60
%
%
%
Input Data:
     Input Logic High3
     Input Logic Low3
VIH
VIL
2.0
-
-
0.8
V
V
Control Voltage Bandwidth (-3 dB, VC=2.50 V)
BW
50
-
kHz
Sensitivity @ VC=VO
F/VC
See Figure 4.
ppm/V
Loss of Signal Indication5:
     Output Logic High3
     Output Logic Low3
LOS
VOH
VOL
2.5
-
-
0.5
V
V
Nominal Output Frequency on Loss of Signal:
     Output 1
     Output 2
OUT1
OUT2
-75 ppm
-75 ppm
75 ppm
75 ppm
ppm from fo1
ppm from fo2
Phase Detector Gain
KD
-0.53 x Data Density
rad/V
1. For input RZ data, Manchester encoded data, and input clock recovery applications, the output clock must run at two times the input rate to ensure that the input is clocked correctly. Since the output clock has a maximum frequency of 52.0 MHz, these inputs are limited to a maximum rate of 26 MHz.
2. OUT2 is a binary submultiple of OUT1, as specified in the device code shown in Figure 6. OUT2 may also be disabled.
3. Figure 2 defines these parameters. Figure 3 illustrates the equivalent five-gate MTTL load and operating conditions under which these parameters are specified and tested.
4. Symmetry is the ON TIME/PERIOD in percent with VS=1.4 V for TTL, per Figure 2.
5. A loss of signal (LOS) indicator is set to a logic high if no transitions are detected at DATAIN after 256 clock cycles. As soon as a transition occurs at DATAIN, LOS is set to a logic low.




Absolute Pull

Absolute pull range (APR) is specified by the fourth character of the product code. The APR is the minimum guaranteed frequency shift from FO over variations in temperature, aging, power supply, and load. Both frequency and environment limit the specified APR. The total pull range for the VCXO contained in the TRU050 is typically between 200 ppm and 400 ppm.

A 50 ppm APR TRU050 fully tracks a 50 ppm source oscillator or any other 50 ppm reference over the operating temperature range, life of the product, power supply and measurement variations.

Parameter
Symbol
Min
Max
Unit
Absolute Frequency Pull Range
APR
-APR
APR
ppm from FO




Outline Diagram
Thru-Hole
Thru-hole


Surface Mount
Surface Mount




Pin Information

Pin#
Symbol
Type
Function
1
VC
|
 Control voltage input to internal voltage-controllable crystal oscillator (VCXO).
2
OPN
|
 Negative input terminal to internal operational amplifier.
3
OPOUT
O
 Output terminal of internal operational amplifier.
4
OPP
|
 Positive input terminal to internal operational amplifier.
5
LOSIN
|
 With LOSIN set to a logic high, the external input to the VCXO (VC) is disabled and the VCXO returns to its nominal center frequency. With LOSIN set to logic low, the external input to the VCXO is enabled. The LOSIN input has an internal pull-down resistor.
6
PHO
O
 Output signal produced by phase detector and used as VC at Pin1.
7
DATAIN
|
 Input data stream to phase detector (TTL switching thresholds).
8
GND
|
 Circuit and cover ground.
9
CLKIN
|
 Input clock signal to phase detector (TTL switching thresholds)..
10
LOS
O
 Loss of signal indicator is set to a logic high if no transitions are detected at DATAIN after 256 clock cycles. As soon as a transition occurs at DATAIN, LOS is set to a logic low.
11
RCLK
O
 TTL compatible recovered clock.
12
RDATA
O
 TTL compatible recovered data stream.
13
OUT2
O
 Divided version of internal VCXO output clock (TTL).
14
HIZ
|
 When set to a logic low, output pins OUT1, OUT2, RCLK, and RDATA buffers are set to high-impedance state. When set to a logic high or no connect, the device functions and output pins OUT1, OUT2, RCLK, and RDATA are active. This input has an internal pull-up resistor.
15
OUT1
O
 Output clock of internal VCXO (TTL).
16
VDD
|
 5 V ± 10% supply voltage. (3.3 V option available)




Standard Frequencies* (MHz) using OUT 1
12.032 12.288 12.624 13.824 16.000 16.128 16.384
16.777 16.896 17.920 18.432 18.936 19.440 20.000
20.480 22.1184 22.579 24.576 24.704 25.000 25.248
28.000 30.720 32.000 32.768 33.330 34.368 38.880
40.000 40.960 41.2416 41.943 44.736 47.457 49.152
49.408 50.000 51.840 65.536


Standard Frequencies* (MHz) using OUT 2
1.000 1.024 1.544 2.048 3.088 3.240 4.032
4.096 4.1925 4.224 5.592 6.016 6.144 6.312
6.480 6.912 7.680 8.000 8.192 8.448 8.960
9.468 9.720 10.000 10.240 11.0592 12.352 12.500
12.960 14.000 16.000 16.384 16.665 19.440 20.000
20.6208 20.9715 22.368 23.7285 24.576 24.704 25.920
32.768

* Other frequencies available upon request.